A recent development in semiconductor processing is the tri-gate transistor, or non-planar transistor. A tri-gate transistor includes a thin semiconductor body (e.g., a silicon fin) formed on a substrate and having a top surface and two sidewall surfaces perpendicular to the top surface. A gate structure is formed on the substrate and the silicon fin perpendicular to the silicon fin. Source and drain regions are formed in the fin on opposite sides of the gate structure. Because the gate structure surrounds the silicon fin on the three surfaces, the transistor essentially has three separate gates. These three separate gates provide three separate channels for electrical signals to travel, thus effectively tripling the conductivity as compared to a conventional planar transistor.
Tri-gate transistors generally have superior performance to bulk gate devices. This is due to the proximity of the top and side gates relative to one another which causes full depletion and results in steeper sub-threshold gradients (SG) and smaller drain induced barrier lowering (DIBL). The SG and DIBL typically are used to determine short-channel effects (SCEs) in a transistor. In general, it is desired that SCEs are low such that the transistor off-state leakage current, IOFF (i.e., a current flowing between source and drain regions when a transistor is in an OFF state), remains as low as possible. A steeper SG and/or reduced DIBL indicates lower IOFF, and thus smaller and better SCEs.
In the fabrication of tri-gate transistors, the silicon fin is subjected to ion implantation, or doping. In one method, the silicon fin is doped at a 45° angle. This results in the sidewalls being doped at approximately one-half the dose as the top surface of the silicon fin. In a variation of this method, the silicon fin is doped at both a 60° angle and a 30° angle. This results in the sidewalls and top surface being doped equally, but the sidewall is now doped at approximately two-thirds of the desired depth and one-third the desired depth on the top surface of the silicon fin. Additionally, when a substrate comprises a plurality of silicon fins on the same surface, one silicon fin can create a shadow on another silicon fin situated approximately perpendicular and approximately adjacent to one another in angled doping, which results in variable doping on the surfaces of the silicon fins. In yet another method, the substrate and silicon fin(s) are electrically grounded and subjected to plasma doping. This results in greater doping on the top surfaces of the silicon fin(s) relative to the sidewalls. The uneven doping of the silicon fin results in a change in resistance of the current.